Clock tree synthesis method

ABSTRACT

The invention discloses a clock tree synthesis method including steps of: determining a driving strength of a clock cell; determining a reserved space corresponding to the clock cell according to the driving strength; generating the clock cell and the reserved space, wherein the reserved space is adjacent to the clock cell; setting a decoupling capacitor filler cell in the reserved space, wherein the area and/or capacitance of the decoupling capacitor filler cell are/is associated with the driving strength; and fixing the attribute(s) of the clock cell and the attribute(s) of the decoupling capacitor filler cell.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to clock trees, and, more particularly, toa clock tree synthesis (CTS) method.

2. Description of Related Art

Clock trees are widely used in modern integrated circuits. FIG. 1 is aschematic diagram of a conventional circuit layout that includes twoclock trees: the clock tree 112 and the clock tree 122. The clock tree112 includes a plurality of clock cells 115, and the clock tree 122includes a plurality of clock cells 125. A clock cell is, for example,an inverter or a buffer. The clock tree 112 is electrically connected tothe phase-locked loop (PLL) 110 that provides clock to the registers 132and 134 via the clock tree 112. The clock tree 122 is electricallyconnected to the PLL 120 that provides clock to the registers 136 and138 via the clock tree 122. The logic circuit 140 is coupled between theregister 132 and the register 134 and forms a data path therebetween.Components such as the analog circuit 150, the memory 160, and theoutput/input circuit 170 are also included in the circuit. For reason ofsimplicity, the wirings connecting the analog circuit 150, the memory160, and the output/input circuit 170 with other components are notshown in FIG. 1.

Before a clock tree is synthesized, a floorplan step and a placementoptimization step are performed. Floorplan refers to the arrangement ofthe components. Placement optimization refers to the optimization of thedata paths. Since the width of the polycrystal is getting smaller as theprocess advances, an electromigration effect may occur when clock cellswith strong driving strength are close to each other. Moreover, the IRdrop issue must also be taken into consideration in the circuit designas the power consumption of the clock cells gets higher as a result ofincreased chip clock (i.e., higher toggle rate). Accordingly, the clockcells are arranged in a way that they are not too close to each other toreduce the probability that the circuit fails the electromigration testand the IR drop test. However, parameters corresponding to the spacesreserved between the clock cells, such as the clock cell spacing, arenot mandatory for the physical implementation tool, that is, theparameters are soft constraints rather than hard constraints. As aresult, even if appropriate spaces between the clock cells are reservedin the floorplan step, the spaces may become too small after the clocktree is synthesized, causing the circuit to fail the test.

Therefore, there is a demand for a clock tree synthesis (CTS) method toensure that there is sufficient space between the clock cells or betweenthe clock cells and other elements after the clock tree is synthesized.

SUMMARY OF THE INVENTION

In view of the issues of the prior art, an object of the presentinvention is to provide a clock tree synthesis method, so that a circuitis more likely to pass the electromigration test and the IR drop test.

A clock tree synthesis method is provided. The clock tree synthesismethod includes the steps of: selecting a clock cell; setting a keep-outmargin for the clock cell; performing clock tree synthesis to generatethe clock cell and a reserved space adjacent to the clock cell, whereinthe size of the reserved space corresponds to the keep-out margin;disposing a decoupling capacitor filler cell in the reserved space,wherein an area and/or capacitance of the decoupling capacitor fillercell are/is related to the keep-out margin; and fixing an attribute ofthe clock cell and an attribute of the decoupling capacitor filler cell.

A clock tree synthesis method is also provided. The clock tree synthesismethod includes the steps of: determining a driving strength of a clockcell; determining a reserved space corresponding to the clock cellaccording to the driving strength; generating the clock cell and thereserved space, wherein the reserved space is adjacent to the clockcell; disposing a decoupling capacitor filler cell in the reservedspace, wherein an area and/or capacitance of the decoupling capacitorfiller cell are/is related to the driving strength; and fixing anattribute of the clock cell and an attribute of the decoupling capacitorfiller cell.

The clock tree synthesis method of the present invention can ensure thatthere is sufficient space between a clock cell and another clock cell orbetween a clock cell and other elements after the clock tree issynthesized (i.e., after the clock cell is formed). Electromigration andIR drop are less likely to happen in the clock tree generated accordingto the clock tree synthesis method of the present invention than in theclock tree of the conventional technology, so that the clock tree of thepresent invention is easier to pass the test, and the service life andstability of the circuit can be improved.

These and other objectives of the present invention no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiments withreference to the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic diagram of a conventional circuit layout.

FIG. 2 illustrates a flow chart of a clock tree synthesis methodaccording to an embodiment of the present invention.

FIG. 3 illustrates a top view of a clock cell accompanied by a reservedspace.

FIG. 4 illustrates a schematic diagram of a clock cell and a decouplingcapacitor adjacent to the clock cell.

FIG. 5 illustrates a detailed flow of step S240 of FIG. 2.

FIG. 6 illustrates a flow chart of a clock tree synthesis methodaccording to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following description is written by referring to terms of thistechnical field. If any term is defined in this specification, such termshould be explained accordingly. In addition, the connection betweenobjects or events in the below-described embodiments can be direct orindirect provided that these embodiments are practicable under suchconnection. Said “indirect” means that an intermediate object or aphysical space exists between the objects, or an intermediate event or atime interval exists between the events.

The disclosure herein includes a clock tree synthesis method. Some orall of the processes of the clock tree synthesis method may beimplemented by software and/or firmware. A person having ordinary skillin the art can choose components or steps equivalent to those describedin this specification to carry out the present invention, which meansthat the scope of this invention is not limited to the embodiments inthe specification.

FIG. 2 is a flow chart of a clock tree synthesis method according to anembodiment of the present invention. The floorplan step (step S210)includes selecting a clock cell from a clock cell library. This stepdetermines the driving strength of the clock cell. In other words, thisstep selects the clock cell according to the required driving strength.However, in order to pass the electromigration test and the IR droptest, most of the time this step does not select the clock cell with thestrongest driving strength. After the step S210 is completed, the methodperforms placement optimization (step S215) and then sets a keep-outmargin of the clock cell (step S220). Step S220 can be carried out onthe physical implementation tool through a “set_keepout_margin”instruction or an equivalent instruction. For the physicalimplementation tool, this keep-out margin is a hard constraint indicatesthe size of the reserved space adjacent to the clock cell. For example,the keep-out margin may indicate the area, side length, or perimeter ofthe reserved space. This keep-out margin is related to the drivingstrength of the clock cell. In some embodiments, the stronger thedriving strength of the clock cell is, the larger the keep-out marginis, and the weaker the driving strength of the clock cell is, thesmaller the keep-out margin is. In general, the greater the drivingstrength of the clock cell is, the larger the area of the clock cell is,meaning that the area of the reserved space can be proportional to thearea of the clock cell. In other words, the keep-out margin can also beset according to the size of the clock cell. A larger reserved space canreceive a larger decoupling capacitor.

Next, clock tree synthesis is performed according to the selected clockcell and the set keep-out margin, so as to generate the clock cell andthe reserved space (step S230). FIG. 3 is a top view of a clock cellaccompanied by a reserved space. The reserved space 315 is adjacent tothe clock cell 310. The example of FIG. 3 approximates the clock cell310 as a quadrilateral element, but the clock cell 310 can also beapproximated as other polygons, and the reserved space 315 may bearranged on any side of the clock cell 310. All the clock cells thathave been set to have the keep-out margin in step S220 are accompaniedby the reserved space after step S230 is completed. Since the keep-outmargin is treated as a hard constraint by the physical implementationtool, when performing the clock tree synthesis step the physicalimplementation tool determines that the clock cell that has been set tohave the keep-out margin needs to occupy a relatively large space.

Next, a decoupling capacitor filler cell is provided for the clock cellthat has been set to have the keep-out margin, that is, a decouplingcapacitor is disposed (or inserted) in the reserved space 315 (stepS240). The area and/or capacitance of the decoupling capacitor are/isrelated to the reserved space 315 (i.e., related to the keep-outmargin). In some embodiments, the larger the keep-out margin or thereserved space is, the larger the area and capacitance of the decouplingcapacitor are. In other words, the decoupling capacitor can also beselected according to the driving strength or size of the clock cell.

After step S240 is completed, the clock cell is electrically connectedto the decoupling capacitor. FIG. 4 shows a schematic diagram of a clockcell and a decoupling capacitor adjacent to the clock cell.Electrically, the decoupling capacitor 415 is connected in parallel withthe clock cell 410 (“IN” is the input of the clock cell 410, and “OUT”is the output of the clock cell 410). The decoupling capacitor 415 canreduce dynamic drop of the voltage source VDD, thus reducing the effectof the IR drop. Next, routing is performed to appropriately connect theelements on the circuit (step S250), and finally optimization isperformed after routing (step S260) and then the filler cells areinserted (step S270). Steps S250 to S270 are conventional steps, and thedetails are omitted for brevity. However, this invention is differentfrom the prior art in that the conventional clock tree synthesis methoddoes not have any decoupling capacitor filler cell formed in the circuit(i.e., the clock cell is not connected in parallel with any decouplingcapacitor) before steps S250 to S270, whereas in the present inventionthe decoupling capacitor filler cell has already been formed in thecircuit (formed at step S240) before steps S250 to S270 are performed.

FIG. 5 is a detailed flow of step S240. After the synthesis of the clocktree is completed and before the keep-out margin is removed, multiplefiller cells are inserted in the circuit (step S510). The filler cell isa structure that contains polycrystals but no metal. After step S510 iscompleted, non-occupied parts of the circuit (i.e., areas not taken bythe clock cells, the reserved spaces, and the components (including butnot limited to the PLL, register, logic circuit, analog circuit, memory,and output/input circuit)) are filled with filler cells. The keep-outmargins are then removed (step S520). The instruction on the physicalimplementation tool corresponding to step S520 is“remove_keepout_margin” (or an equivalent instruction). For the physicalimplementation tool, the reserved space on the circuit is no longeroccupied after step S520 is completed, that is, from the perspective ofthe physical implementation tool, there is no component disposed in thereserved space. Next, the decoupling capacitor filler cell(s) is(are)disposed (or inserted) in the reserved space(s) (step S530). After stepS530 is completed, the clock cell(s) that has(have) been set to have thekeep-out margin (i.e., the clock cell(s) having an adjacent reservedspace) is(are) connected in parallel with the decoupling capacitor(s)(as shown in FIG. 4) Finally, the filler cell(s) is(are) removed (stepS540), and then the attribute(s) of the clock cell(s) and theattribute(s) of the decoupling capacitor filler cell(s) are fixed (stepS550). Step S550 aims to make the positions of the clock cell(s) and thedecoupling capacitor filler cell(s) fixed and therefore not change inthe subsequent steps. The attribute(s) referred to in step S550include(s), for example, position information of the clock cell(s) andthe decoupling capacitor filler cell(s).

FIG. 6 is a flow chart of a clock tree synthesis method according toanother embodiment of the present invention. First, the driving strengthof the clock cell is determined (step S610), that is, an appropriateclock cell is selected according to requirements (e.g., the size of theclock tree, the position of the clock cell, and the like). Then, thereserved space of the clock cell is determined according to the drivingstrength of the clock cell (step S620), that is, the size of thereserved space is related to the driving strength and/or area of theclock cell. A clock cell and a reserved space are then generated withthe reserved space adjacent to the clock cell (as shown in FIG. 3) (stepS630). Next, a decoupling capacitor filler cell is disposed (orinserted) in the reserved space (step S640). The area and/or capacitanceof the decoupling capacitor filler cell are/is related to the drivingstrength and/or area of the clock cell. The detailed flow of step S640is shown in FIG. 5. After step S640 is completed, steps S250 to S270 areperformed.

In some embodiments, the clock cell 310 and the reserved space 315 ofFIG. 3 are closely adjacent to each other, and there is no space formore filler cells to be inserted between them.

The invention can cause the physical implementation tool to take intoconsideration, when the clock tree is being synthesized, the influencesof the inserted decoupling capacitor filler cell on clock latency andclock skew of the circuit. Therefore, the result obtained when the clocktree synthesis is completed can be consistent with the result obtainedafter the decoupling capacitor filler cell(s) is(are) disposed (orinserted). By setting the keep-out margin (i.e., setting the reservedspace) before the clock tree synthesis step, and setting the decouplingcapacitor filler cell(s) and fixing the attribute(s) of the decouplingcapacitor filler cell(s) and the clock cell(s) before routing, a certainspace between the clock cell and other clock cells or components can beensured by the utilization of the decoupling capacitor(s), therebyleading to more evenly distributed clock cells. Furthermore, since thecapacitor of the decoupling capacitor filler cell per se can reduce IRdrop, the present invention can effectively mitigate theelectromigration and/or IR drop issue(s) in the region in which theclock cell(s) is(are) set.

Since a person having ordinary skill in the art can appreciate theimplementation detail and the modification thereto of the present methodinvention of through the disclosure of the device invention of, repeatedand redundant description is thus omitted. Please note that there is nostep sequence limitation for the method inventions as long as theexecution of each step is applicable. Furthermore, the shape, size, andratio of any element and the step sequence of any flow chart in thedisclosed figures are exemplary for understanding, not for limiting thescope of this invention.

The aforementioned descriptions represent merely the preferredembodiments of the present invention, without any intention to limit thescope of the present invention thereto. Various equivalent changes,alterations, or modifications based on the claims of the presentinvention are all consequently viewed as being embraced by the scope ofthe present invention.

What is claimed is:
 1. A clock tree synthesis method comprising:selecting a clock cell; setting a keep-out margin for the clock cell;performing clock tree synthesis to generate the clock cell and areserved space adjacent to the clock cell, wherein the size of thereserved space corresponds to the keep-out margin; inserting, in areasother than the clock cell and the reserved space, a plurality of fillercells containing polycrystals; removing the keep-out margin; inserting adecoupling capacitor filler cell in the reserved space, wherein an areaand/or capacitance of the decoupling capacitor filler cell are/isrelated to the keep-out margin; removing the filler cells; and fixing aposition of the clock cell and a position of the decoupling capacitorfiller cell.
 2. The method of claim 1, wherein the keep-out margin isset according to a driving strength of the clock cell.
 3. The method ofclaim 2, wherein the stronger the driving strength is, the larger thekeep-out margin is, and the weaker the driving strength is, the smallerthe keep-out margin is.
 4. The method of claim 1 further comprising:performing routing and optimization after the position of the clock celland the position of the decoupling capacitor filler cell are fixed; andinserting a plurality of filler cells after routing.
 5. A clock treesynthesis method comprising: determining a driving strength of a clockcell; determining a reserved space corresponding to the clock cellaccording to the driving strength; generating the clock cell and thereserved space, wherein the reserved space is adjacent to the clockcell; inserting, in areas other than the clock cell and the reservedspace, a plurality of filler cells containing polycrystals; inserting adecoupling capacitor filler cell in the reserved space, wherein an areaand/or capacitance of the decoupling capacitor filler cell are/isrelated to the driving strength; removing the filler cells; and fixing aposition of the clock cell and a position of the decoupling capacitorfiller cell.
 6. The method of claim 5, wherein the stronger the drivingstrength is, the larger the reserved space and the decoupling capacitorfiller cell are, and the weaker the driving strength is, the smaller thereserved space and the decoupling capacitor filler cell are.
 7. Themethod of claim 5 further comprising: performing routing andoptimization after the position of the clock cell and the position ofthe decoupling capacitor filler cell are fixed; and inserting aplurality of filler cells after routing.